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74ABT16373 16-Bit Transparent D-Type Latch with 3-STATE Outputs
March 1994 Revised May 2005
74ABT16373 16-Bit Transparent D-Type Latch with 3-STATE Outputs
General Description
The ABT16373 contains sixteen non-inverting latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear transparent to the data when the Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the outputs are in high Z state.
Features
s Separate control logic for each byte s 16-bit version of the ABT373 s High impedance glitch free bus loading during entire power up and power down cycle s Non-destructive hot insertion capability s Guaranteed latch-up protection
Ordering Code:
Order Number 74ABT16373CSSC 74ABT16373CMTD Package Number MS48A MTD48 Package Description 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names OEn LEn D0-D15 O0-O15 Description Output Enable Input (Active LOW) Latch Enable Input Data Inputs Outputs
(c) 2005 Fairchild Semiconductor Corporation
DS011666
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74ABT16373
Functional Description
The ABT16373 contains sixteen D-type latches with 3-STATE standard outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable (LEn) input is HIGH, data on the Dn enters the latches. In this condition the latches are transparent, i.e., a latch output will change states each time its D input changes. When LEn is LOW, the latches store information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LEn. The 3STATE standard outputs are controlled by the Output Enable (OEn) input. When OEn is LOW, the standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches.
Truth Tables
Inputs LE1 X H H L OE1 H L L L Inputs LE2 X H H L OE2 H L L L D8-D15 X L H X D0-D7 X L H X Outputs O0-O7 Z L H (Previous) Outputs O8-O15 Z L H (Previous)
H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance Previous previous output prior to HIGH-to-LOW transition of LE
Logic Diagrams
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74ABT16373
Absolute Maximum Ratings(Note 1)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-Off State in the HIGH State Current Applied to Output in LOW State (Max) DC Latchup Source Current: OE Pin (Across Comm Operating Range) Other Pins Over Voltage Latchup (I/O) twice the rated IOL (mA)
65qC to 150qC 55qC to 125qC 55qC to 150qC 0.5V to 7.0V 0.5V to 7.0V 30 mA to 5.0 mA
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate ('V/'t) Data Input Enable Input 50 mV/ns 20 mV/ns
40qC to 85qC 4.5V to 5.5V
0.5V to 5.5V 0.5V to VCC
350 mA 500 mA
10V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol VIH VIL VCD VOH VOL IIH IBVI IIL VID Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input LOW Current Input Leakage Test 4.75 2.5 2.0 0.55 1 1 7 V Min 2.0 0.8 Typ Max Units V V V Min Min Min Max Max Max 0.0 VCC Conditions Recognized HIGH Signal Recognized LOW Signal IIN IOH IOH IOL VIN VIN VIN VIN VIN IID
1.2
18 mA 3 mA 32 mA
64 mA 2.7V (Note 3) VCC 7.0V 0.5V (Note 3) 0.0V 1.9 PA
PA PA PA
V
1 1
All Other Pins Grounded IOZH IOZL IOS ICEX IZZ ICCH ICCL ICCZ ICCT Output Leakage Current Output Leakage Current Output Short-Circuit Current Output HIGH Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current Additional ICC/Input Outputs Enabled Outputs 3-STATE Outputs 3-STATE ICCD Dynamic ICC (Note 3)
Note 3: Guaranteed, but not tested. Note 4: For 8 bits toggling, ICCD 0.8 mA/MHz.
10
PA PA
mA
0 5.5V VOUT 0 5.5V VOUT Max Max 0.0 Max Max Max VOUT VOUT VOUT
2.7V; OE 0.5V; OE 0.0V VCC
2.0V 2.0V
10 100 275
50 100 2.0 62 2.0 2.5 2.5 2.5
PA PA
mA mA mA mA mA mA mA/
5.5V; All Others GND
All Outputs HIGH All Outputs LOW OE VI V CC VCC 2.1V VCC 2.1V V CC 2.1V VCC
All Others at VCC or GND Max Enable Input VI Data Input VI
All Others at VCC or GND No Load 0.15 MHz Max Outputs Open, LE OE GND, (Note 4)
One Bit Toggling, 50% Duty Cycle
3
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74ABT16373
AC Electrical Characteristics
(SOIC and SSOP Packages) TA Symbol Parameter Min tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Output Disable Time Propagation Delay Dn to On Propagation Delay LE to On Output Enable Time 1.4 1.4 1.7 1.7 1.1 1.5 2.4 1.6 VCC CL
25qC 5.0V
50 pF Typ Max 5.6 5.6 6.0 5.5 6.1 5.6 7.1 6.5
TA VCC
40qC to 85qC
4.5V to 5.5V 50 pF Max 5.6 5.6 6.0 5.5 6.1 5.6 7.1 6.5 ns ns ns ns CL Units
Min 1.4 1.4 1.7 1.7 1.1 1.5 2.4 1.6
AC Operating Requirements
(SOIC and SSOP Packages) TA Symbol Parameter Min fTOGGLE tS(H) tS(L) tH(H) tH(L) tW(H) Maximum Toggle Frequency Setup Time, HIGH or LOW Dn to LE Hold Time, HIGH or LOW Dn to LE Pulse Width, LE HIGH 1.5 1.5 1.0 1.0 3.0 VCC CL
25qC 5.0V
50 pF Typ 100 Max
TA VCC
40qC to 85qC
4.5V to 5.5V 50 pF Max MHz CL Units
Min 1.5 1.5 1.0 1.0 3.0
ns ns ns
Capacitance
Symbol CIN COUT (Note 5) Parameter Input Capacitance Output Capacitance Typ 5 11
1 MHz, per MIL-STD-883, Method 3012.
Units pF pF VCC VCC 0V 5.0V
Conditions (TA 25qC)
Note 5: COUT is measured at frequency f
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74ABT16373
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A
5
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74ABT16373 16-Bit Transparent D-Type Latch with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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